Mapping Algorithms for Network on Chip

Abstract

Network on chip is gaining popularity as the time is going on, due to increasing communication. As the number of transistors growing the network on chip is becoming complex. To reduce the complexity, 3D NoC was there but still improvements are required as more the number of wires more is the complexity and lesser is the speed involved. So the aim of this research is to find such an mapping algorithm which can map the cores or task to a topology in such a way that less energy is consumed, less time for communication, faster speed of accessing, cores with maximum communication are brought closer making the network less complex. To achieve these properties, the existing mapping approaches are mentioned in this report. Keeping the drawbacks of existing approaches in mind my aim is to find such a mapping technique which suits all the QoS requirements and is best among all the existing approaches.